In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions to submicron levels (e.g., below 0.35 microns) on semiconductor substrates. In order to accomplish such high device density, smaller features sizes are required. The smaller feature sizes may include the width and spacing of metal interconnecting lines, spacing and diameter of contact holes, width of interlayer dielectric materials, and the surface geometry, such as corners and edges of various features.
Dielectric materials used in film layers can directly affect the performance (e.g., operational speed) of the semiconductor device. Silicon dioxide (SiO2) has been typically used as an interlayer dielectric material (ILD). SiO2 has, however, been replaced with other dielectric materials with a lower dielectric constant (k) to achieve greater device operational speeds. Reducing the dielectric constant of the dielectric material reduces capacitive losses between adjacent conductors because the dielectric material stores less electric field and, therefore, takes less time to charge. This allows for an increase in speed performance of the adjacent conductors. Low-k dielectrics, however, can be potentially prone to damage due to stresses induced during formation and after packaging of the semiconductor device since low-k dielectrics can be structurally weak.